1. Field of the Invention
The present invention relates to a method for producing a semiconductor device and a semiconductor device.
2. Description of the Related Art
The degree of integration of semiconductor integrated circuits, in particular, integrated circuits using MOS transistors, has been continuously increasing. With this trend toward a higher degree of integration, the size of MOS transistors in integrated circuits has been reduced to the order of nanometers. Such reduction in the size of MOS transistors makes it difficult to suppress leakage current. Since a certain amount of current needs to be provided, it is difficult to achieve reduction in the area occupied by circuits, which has been problematic. In order to address such a problem, a Surrounding Gate Transistor (hereafter referred to as “SGT”), which has a structure in which a source, a gate, and a drain are arranged in a direction perpendicular to a substrate and a gate electrode surrounds a pillar-shaped semiconductor layer, has been proposed (for example, refer to Japanese Unexamined Patent Application Publication No. 2-71556, Japanese Unexamined Patent Application Publication No. 2-188966, and Japanese Unexamined Patent Application Publication No. 3-145761).
In an existing SGT production method, a mask for forming silicon pillars is used to form silicon pillars including pillar-shaped nitride hard masks, a mask for forming a planar silicon layer is used to form a planar silicon layer under the silicon pillars, and a mask for forming gate lines is used to form gate lines (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317).
In other words, three masks are used to form silicon pillars, a planar silicon layer, and gate lines.
Also, in an existing SGT production method, in order to establish a connection between an upper portion of a planar silicon layer and metal wiring, a deep contact hole is formed (for example, refer to Japanese Unexamined Patent Application Publication No. 2009-182317). With reduction in the size of devices, the aspect ratio (depth/diameter) of contact holes increases. This increase in the aspect ratio causes a decrease in the etching rate. Also, with reduction in the size of a pattern, the thickness of the resist film decreases. Such a thin resist film is itself etched during etching, which makes it difficult to form deep contact holes.
In existing MOS transistors, in order to successfully perform a metal gate process and a high-temperature process, a metal gate-last process of forming a metal gate after a high-temperature process is used for actual products (IEDM2007 K. Mistry et. al, pp 247-250). In production of an SGT, a gate is formed of polysilicon; an interlayer insulating film is subsequently deposited; chemical mechanical polishing is performed to expose the polysilicon gate; the polysilicon gate is etched; and metal is subsequently deposited. Thus, also in the production of an SGT, in order to successfully perform a metal gate process and a high-temperature process, a metal gate-last process of forming a metal gate after a high-temperature process needs to be used.
In the metal gate-last process, after a polysilicon gate is formed, a diffusion layer is formed by ion implantation. However, in an SGT, the upper portion of the pillar-shaped silicon layer is covered with a polysilicon gate. Accordingly, it is necessary to find a way to form a diffusion layer.
With a decrease in the thickness of silicon pillars, since silicon has a density of 5×1022 atoms/cm3, it becomes difficult to make impurities be present in silicon pillars.
In existing SGTs, it has been proposed that, while the channel concentration is set to a low impurity concentration of 1017 cm−3 or less, the work function of the gate material is changed to control the threshold voltage (for example, refer to Japanese Unexamined Patent Application Publication No. 2004-356314).
A planar MOS transistor has been disclosed in which a sidewall for an LDD region is formed of a polycrystalline silicon of the same conductivity type as that of the lightly doped layer and the surface carriers of the LDD region are induced by the work-function difference between the sidewall and the LDD region, so that the impedance of the LDD region can be reduced, compared with oxide film sidewall LDD MOS transistors (for example, refer to Japanese Unexamined Patent Application Publication No. 11-297984). This publication states that the polycrystalline silicon sidewall is electrically insulated from the gate electrode. This publication also shows that, in a drawing, the polycrystalline silicon sidewall and the source-drain are insulated from each other with an interlayer insulating film.
In existing MOS transistors, in order to decrease a parasitic capacitance between a gate line and a substrate, a first insulating film is used. For example, in a FINFET (IEDM2010 CC. Wu, et. al, 27.1.1-27.1.4), a first insulating film is formed around a single fin-shaped semiconductor layer and the first insulating film is subjected to etch back to expose the fin-shaped semiconductor layer, so that the parasitic capacitance between the gate line and the substrate is decreased. Also for SGTs, in order to decrease the parasitic capacitance between a gate line and a substrate, a first insulating film needs to be used. Since an SGT includes, in addition to a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, it is necessary to find a way to form the pillar-shaped semiconductor layer.